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[VHDL-FPGA-Verilog] syn_fifo

Description: Verilog，syn_fifo ，内含详细说明，同步FIFO为TPRAM-Verilog, syn_fifo, containing detailed instructions for synchronous FIFO TPRAM
Platform: | Size: 160768 | Author: 杨莉莉 | Hits:

[VHDL-FPGA-Verilog] sync_fifo

Description: 同步fifo实现代码，包括的参数：数据宽度、fifo深度、地址宽度；状态信息包括：full, empty。-verilog RTL code which implement a synchronous FIFO function with data width, fifo depth, address pointer width parameterized.
Platform: | Size: 1024 | Author: BaiLi | Hits:

[VHDL-FPGA-Verilog] async_fifo_prj

Description: Verilog语言写的异步fifo，包含随机数产生电路和testbentch,直接可用于实际工程中。代码为华为内部代码。相信你会喜欢。-Verilog language used to write asynchronous fifo, including random number generation circuit and testbentch, can be used directly in the actual project. Code for Huawei internal code. I believe you will like it.
Platform: | Size: 27829248 | Author: allcot | Hits:

[VHDL-FPGA-Verilog] A_FIFO

Description: 自己编写的Verilog 异步fifo 有一定的个参考价值 -Verilog 异步 Fifo
Platform: | Size: 459776 | Author: john | Hits:

[VHDL-FPGA-Verilog] S_FIFO

Description: 自己编写的同步Verilog FiFO 还是不错的 可以-Verilog 同步 FIFO
Platform: | Size: 637952 | Author: john | Hits:

[VHDL-FPGA-Verilog] rx_tx_demo

Description: 用verilog实现的少量字符串的连续收发，添加了FIFO模块，稍微修改下就可以使用。-Receive a small amount of a continuous string of verilog implementation, added FIFO module, can be used under slightly modified.
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Verilog] ABOUT_FIFO

Description: 这是FPGA黑金开发板的教材，驱动篇关于FIFO读写的部分，通过VERILOG语言编写程序，实现先入先出，内附有PDF教材及相应的源代码。-This is the black gold FPGA development board materials, drive to read and write papers on FIFO part by VERILOG programming language, to achieve first-in first-out, Enclosed PDF materials and the corresponding source code.
Platform: | Size: 5404672 | Author: 周燕 | Hits:

[VHDL-FPGA-Verilog] HWL_ASYNC_FIFO_DRAM_BA

Description: asynchronous fifo based on distributed RAM. xilinx fpga. VErilog language.
Platform: | Size: 2048 | Author: D | Hits:

[VHDL-FPGA-Verilog] DWC_mctl_ddr_fifo

Description: ASIC设计中各种同步异步的FIFO实现的verilog source code, 参数可配置 -almost all kinds of FIFO with verilog source code, parametes configuration
Platform: | Size: 10240 | Author: moses lee | Hits:

[VHDL-FPGA-Verilog] fifo_pipeline_booth_multiplier

Description: fifo_pipeline_modified_booth_multiplier一个使用FIFO的Booth乘法器，并且使用了流水线描述方式，本程序给予verilog 语言-fifo_pipeline_modified_booth_multiplier, a booth multiplier using pipeline technology in verilog HDL language
Platform: | Size: 3072 | Author: 谷雨 | Hits:

[VHDL-FPGA-Verilog] uart_server

Description: 24路串口转1路串口服务程序, 包括FIFO模块，串口接收，发送模块，定时器模块，检测控制模块等。采用Verilog编写-24 way serial ports to 1 serial port, including FIFO module,RX module,TX module, timer module, detection and control module, etc.. Verilog preparation
Platform: | Size: 379904 | Author: wangyu | Hits:

[VHDL-FPGA-Verilog] aFifo

Description: 异步fifo用verilog语言实现的完整代码，适用于数字前端的设计-This implementation is based on the article Asynchronous FIFO
Platform: | Size: 1024 | Author: 张牡丹 | Hits:

[VHDL-FPGA-Verilog] SD_Card

Description: sdhc卡spi扇区读verilog例程。包含sdhc卡初始化模块及一个扇区读模块，扇区读完数据放在一个fifo中缓存，为之后的工作做准备，可以集成到自己的项目中。已经在闪迪8Gsdhc卡上亲测成功-sdhc card sector read spi verilog routine. Initialization module and a read module contains sdhc card sector, the sector read data in a cache fifo in preparation for subsequent work, it can be integrated into your own projects. We have been successful in the pro-test card SanDisk 8Gsdhc
Platform: | Size: 4246528 | Author: 王一鸣 | Hits:

[Other Embeded program] FIFO1

Description: 给出一个位宽16比特，深度为10的异步FIFO的设计，并要求给出空或满的指示信号。要求用Verilog HDL语言设计，并编写测试激励，以及用Modelsim进行功能仿真，验证设计正确性。10个16位的数据　(FIFO的宽度：也就是英文资料里常看到的THE  WIDTH，它指的是FIFO一次读写操作的数据位，就像MCU有8位和16位，ARM 32位等等。FIFO的深度：THE DEEPTH，它指的是FIFO可以存储多少个N位的数据（如果宽度为N）。如一个8位的FIFO，若深度为8，它可以存储8个8位的数据，深度为12，就可以存储12个8位的数据。)-Give a 16 bits wide, depth of 10 asynchronous FIFO design, and requires giving empty or full instructions signal. Request using Verilog HDL language design, and the writing test, and simulation using Modelsim function, validate design is correct. 10 16 bits of data (THE WIDTH of THE FIFO, namely information in English often see THE WIDTH, it refers to a FIFO data read and write operations, as has 8 bit or 16 bit MCU, ARM 32-bit and so on. THE depth of FIFO: THE DEEPTH, it refers to THE FIFO can store many N bits of data (if THE WIDTH is N). If an 8-bit FIFO, if THE depth of 8, it can store 8 8 bits of data, THE depth of 12, 12 8 bits of data to be stored.)
Platform: | Size: 33792 | Author: 江燕子 | Hits:

[VHDL-FPGA-Verilog] asyn_fifo2

Description: 采用Verilog语言，使用FPGA内部IP核FIFO模块，实现串口的传输-Using Verilog language, the use of FPGA IP core internal FIFO module, serial data transmission
Platform: | Size: 3945472 | Author: 杨增健 | Hits:

[Com Port] uartfifo

Description: fifo模式下的uart串口verilog的源程序-fifo mode serial uart verilog source
Platform: | Size: 253952 | Author: boren | Hits:

[Other] sync_fifo

Description: Verilog HDL code for synchronous SRAM FIFO
Platform: | Size: 1024 | Author: sightseeing | Hits:

[VHDL-FPGA-Verilog] uart_fifo_transceiver_verilog

Description: verilog UART FIFO 自发自收 自己验证过 基于EP1C3T开发板的-Verilog UART FIFO internal loopback； tested； based on EP1C3T
Platform: | Size: 711680 | Author: 清水磐石 | Hits:

[VHDL-FPGA-Verilog] uart_fifo

Description: 一份带有FIFO缓存的UART源码，采用verilog编写，实现批量数据的传输，数据缓存量可以通过修改源码中的FIFO的深度来改变。-This is a UART with FIFO. The UART is programmed using verilog, it can transmit or receive batch data. The amount of data buffered can be changed by changing the depth of FIFO.
Platform: | Size: 2048 | Author: 耿瑞 | Hits:

[VHDL-FPGA-Verilog] class_fifo

Description: FPGA内部fifo的调用,使用Verilog对其进行编程-The FPGA internal fifo calls, use Verilog programming on it
Platform: | Size: 11169792 | Author: 李改有 | Hits:
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